An example of prior art semiconductor memory device of this type is shown in FIG. 2. This prior art configuration will now be described by making reference to the figure.
FIG. 2 is a block diagram showing the pertinent portion of a typical prior art semiconductor memory device. It will be noted that, while an actual device has a plurality of address bits, FIG. 2 shows circuits for only two address bits to facilitate the explanation.
As shown, this semiconductor memory device is of a split configuration, i.e., it comprises a plurality of, e.g., two, groups of memory cell blocks, namely a first memory cell block group 10-1 and a second memory cell block group 10-2. The first memory cell block group 10-1 is connected on the address input side to a first group of predecoder input signal lines 12-1 consisting of a plurality of predecoder input signal lines AB1L and AB2L. The second memory cell block group 10-2 is connected on the address input side to a second group of predecoder input signal lines 12-2 consisting of a plurality of predecoder input signal lines AB1R and AB2R. The first and second predecoder input signal groups 12-1 and 12-2 are driven by predecoder input signal generator 20, which is connected to a plurality of address buffers 30-1 and 30-2 via a plurality of address buses AB1 and AB2.
Each of the first and second memory cell block groups 10-1 and 10-2 are comprised of a plurality of memory cell blocks 11, each of which consists of a memory cell array 11a having a decoder, sense amplifiers, etc., and a predecoder 11b for predecoding predecoder input signals AB1L, AB2L, or AB1R, AB2R.
Predecoder input signal generator 20 selectively activates either the first predecoder input signal group 12-1 or the second predecoder input signal group 12-2 in accordance with group select signals .phi..sub.L, .phi..sub.R, and is comprised of a plurality of gate circuits 21, 22 that receive the group select signals .phi..sub.L, .phi..sub.R and address bits AB1, AB2. The outputs of the gate circuits 21, 22 are connected to predecoder input signal groups 12-1, 12-2. Gate circuit 21 consists of a two-input NAND gate 21a, and an inverter 21b. In the same way, gate circuit 22 consists of a two-input NAND gate 22a, and an inverter 22b.
A plurality of address buffers 30-1, 30-2 receive a plurality of external input address bits A1, A2 and pass those signals to the predecoder input signal generator 20 via address buses AB1, AB2.
Notations C1L, C2L, C1R, C2R in FIG. 2 represent the line loads of predecoder input signal lines for transmitting predecoder input signal AB1L, AB2L, AB1R, AB2R, respectively.
FIG. 3 shows a circuit diagram of the pertinent portion of the line load of FIG. 2.
In the figure, only the line loads C1L, C1R for predecoder input signal lines AB1L, AB1R, and inverters 21b, 22b are shown. Inverter 21b is a complementary metal-oxide-semiconductor (hereafter, CMOS) device comprising a p-channel metal-oxide-semiconductor (hereafter, PMOS) transistor 21b-1 and an n-channel metal-oxide-semiconductor (hereafter NMOS) transistor 21b-2. Inverter 22b likewise consists of a CMOS device comprising PMOS transistor 22b-1 and NMOS transistor 22b-2.
FIG. 4 is a timing chart for the device shown in FIG. 2. Referring now to this figure, the operation of the devices depicted in FIG. 2 and FIG. 3 will now be described.
The following description is directed to the operation of the present device responsive to the external input address bits A1, A2 that takes place when the semiconductor memory device has been activated by an external activation signal.
Assume, for example, that either group select signal .phi..sub.L or .phi..sub.R for selecting either the first memory cell block group 10-1 or the second memory cell block group 10-2 is selectively changed from the low level to the high level.
When group select signal .phi..sub.L is at the low level, the first memory cell block group 10-1 is set in the unselected state by an unselect/select means (not shown in the figure). That is, the first memory cell block group 10-1 is in a state in which reading data in and writing data from it is inhibited. At the same time, the first group 12-1 of predecoder input signal lines AB1L, AB2L are clamped at the low level by gate circuit 21, regardless of the data on external input address bits A1, A2. On the other hand, since the group select signal .phi..sub.R is at the high level, the second memory cell block group 10-2 is set in the select state by an unselect/select means (not shown in the figure), and at the same time, the second group 12-2 of predecoder input signal lines AB1R, AB2R asserts high/low level binary logic via gate circuit 22 based on the information input over external input address bits A1, A2.
Next, the operation that takes place when external input address bits A1 and A2 change to the high level and the low level, respectively will be described.
First, when external input address bit A1 is at the low level and external input address bit A2 is at the high level, that information is fetched by address buffers 30-1, 30-2, and appears on address buses AB1, AB2, after a short propagation time delay. Since the address bits on address buses AB1, AB2 are propagated via their respective gate circuits 22, predecoder signal AB1R goes low and predecoder signal AB2R goes high after a short propagation time delay. Consequently, line load C1R on predecoder input signal line AB1R is discharged to the low level through NMOS transistor 22b-2 shown in FIG. 3, and line load C2R on the side of predecoder input signal line AB2R is charged to the high level from power supply voltage Vcc through PMOS transistor 22b-1.
Next, if external input address bit A1 goes from the low level to the high level, and external input address bit A2 goes from the high level to the low level, predecoder input signal AB1R changes from the low to high level and AB2R changes from the high level to low level. As a result, line load C1R is charged via PMOS transistor 22b-1 to the high level from power supply Vcc, and line load C2R is discharged via NMOS transistor 22b-2 to the low level on the power supply Vss (=0) side.
As described above, the selected group of predecoder input signal lines 12-2 assume binary logic based on the external input address information A1, A2. This binary logic is predecoded by predecoder 11b, and is then decoded by the decoder in memory cell array 11a and memory cell locations corresponding to external input address bits A1, A2 are selected. Then, accessing with data can be made at these memory cell locations by means of read/write circuitry, that is not shown in the figure.
However, this conventional semiconductor memory device is associated with the following problem.
In the prior art semiconductor memory device, when external input address bits A1, A2 change all at once either from the high to the low level or from the low to the high level, the Vcc noise (fluctuation) due to the voltage change of the selected second predecoder input signal group is large.
More specifically, when external input address bits A1, A2 change all at once from the high level to the low level (Case 1), the charges on line loads C1R, C2R are discharged all at once to power supply Vss through inverter 22b. When this occurs, since the unselected first group of predecoder input signal lines 12-1 are clamped at the low level, line loads C1L, C2L act as decoupling capacitors for power supply Vss (for restraining the voltage fluctuation by the action of the capacitor), and this serves to alleviate the Vss noise caused by the afore-mentioned discharging. On the other hand, when external input address bits A1, A2 all change from the low level to the high level (Case 2), since line loads C1R, C2R are all charged at once from power supply Vcc through inverter 22b, Vcc noise is generated by this charging current. When this occurs, the unselected first group of predecoder input signal lines 12-1 are clamped at the low level, the same as in Case 1, so line loads C1L, C2L do not act as decoupling capacitors for supply voltage Vcc. As a consequence, the Vcc noise is large.
Along with increased capacity, the integration density of semiconductor memory devices is also continuing to increase. The trend therefore, due to such factors as longer line lengths, is toward increased line loads on predecoder input signal lines. What is more, since Vcc, Vss are also fed to read and write circuits (not shown in the figure) in addition to the line loads, increased noise leads to other problems, such as declining stability of other circuits and slower response speed.